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gbj1
Joined: 08 Feb 2007
Posts: 45
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 Posted: Mon Feb 12, 2007 10:22 pm Post subject: TLB question |
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I feel I'm a noob in MIPS again. I'm doing some reading on its instruction set. I'm wondering if we use these instructions, how will the chip act, error 'FEATURE_NOT_AVAILABLE' ?
TLBR Read Indexed TLB Entry
TLBWI Write Indexed TLB Entry
TLBWR Write Random TLB Entry
TLBP Probe TLB for Matching Entry
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hlide
Joined: 10 Sep 2006
Posts: 750
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| Posted: Tue Feb 13, 2007 5:55 am Post subject: Re: TLB question |
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| gbj1 wrote: | I feel I'm a noob in MIPS again. I'm doing some reading on its instruction set. I'm wondering if we use these instructions, how will the chip act, error 'FEATURE_NOT_AVAILABLE' ?
TLBR Read Indexed TLB Entry
TLBWI Write Indexed TLB Entry
TLBWR Write Random TLB Entry
TLBP Probe TLB for Matching Entry |
First, Allegrex uses a FM MMU (that is a Fixed Mapping Memory Manager Unit) instead of a TLB MMU. Worse, Allegrex doesn't seem to provide a TLB MMU since COP0 registers don't even answer anything when interrogating the TLB-relative registers. I don't try the TLB-relative instructions but i'm quite sure they would raise a Reserved Instruction exception as it would be with trap instructions which are not implemented into Allegrex.
So just forget them. |
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gbj1
Joined: 08 Feb 2007
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| Posted: Tue Feb 13, 2007 10:24 am Post subject: |
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I have heard a sort of memory management unit called 'MPU' (memory protection unit). Allegrex seems to have such a unit to protect its kernel memory.
Sony devs had their unlimited wisdom guided to choose such a chip on their portable game console.
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hlide
Joined: 10 Sep 2006
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| Posted: Tue Feb 13, 2007 4:18 pm Post subject: |
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| gbj1 wrote: | I have heard a sort of memory management unit called 'MPU' (memory protection unit). Allegrex seems to have such a unit to protect its kernel memory.
Sony devs had their unlimited wisdom guided to choose such a chip on their portable game console. |
if you are refering to the ability for protecting the read/write access right to kernel/user code, that is not because of MIPS cpu had this but rather because of a BCU (Bus Control Unit), the registers of which are mapped in memory allegrex (0xBC2000xx if i'm not wrong). You may call it a MPU but it is not its solely function.
I'm not against the fact that Sony drops the TLB management since it would rather slow games down (standard MIPS uses a software TLB management, not a hardware one like ix86).
And Sony never uses the TLB available on PSX for their games too for the same reason. |
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gbj1
Joined: 08 Feb 2007
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| Posted: Tue Feb 13, 2007 6:42 pm Post subject: |
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It also limits the ability to port other operating system other than their own firmware. They made a nice deal with performance and capability.
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