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holger
Joined: 18 Aug 2005
Posts: 204
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 Posted: Sat Oct 01, 2005 8:09 am Post subject: VFPU playground, code generation for gas-unsupported opcodes |
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Hi,
this codelet allows you to emit asm instructions at comile- or runtime, even if the GNU assembler does not yet supports them. Thus we can easily play with the VFPU instruction set. The example below demonstrates this by initializing the VFPU vector register set to zero and then loading an identity matrix in a single instruction.
This raw example only contains some of the most basic instructions and register names (only GPRs, vector and matrix Quadword addressing). Nevertheless you should get the idea how to add new opcodes and play with them.
All opcode and instruction definitions are defined in codegen.h, here they also can get documented. To try, create a directory pspgl/test-vfpu/ and copy the following files into this folder:
Makefile:
| Code: |
ARCH = psp-
CC = $(ARCH)gcc
PSP_INSTALL = ../tools/psp-install
RM = rm -f
PSPPATH := $(shell psp-config --pspsdk-path)
LIBS = -lpspdebug -lpspdisplay -lpspge -lpspsdk -lpspctrl -lm -lc -lpspuser -lpspkernel
CFLAGS = -g -Wall -O2 -MD -I$(PSPPATH)/include
LFLAGS = -g -Wall -O2 -L$(PSPPATH)/lib $(LIBS)
TARGET = test-vfpu
OBJS = main.o
BUILDDATE = $(shell date "+%Y/%m/%d %k:%M:%S")
PSPSDK=$(shell psp-config --pspsdk-path)
all: $(TARGET)
.c.o:
$(CC) $(CFLAGS) -c $<
$(TARGET): $(OBJS)
$(CC) $(OBJS) $(LFLAGS) -o $@
install: all
$(PSP_INSTALL) $(TARGET) --eboot-title="$(TARGET) $(BUILDDATE)"
clean:
$(RM) $(TARGET) *.d *.o *.a *.elf *.sfo EBOOT.PBP
-include $(wildcard *.d) dummy
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codegen.h:
| Code: |
#ifndef __codegen_h__
#define __codegen_h__
/* GPR register set */
#define R_zero 0
#define R_at 1
#define R_v0 2
#define R_v1 3
#define R_a0 4
#define R_a1 5
#define R_a2 6
#define R_a3 7
#define R_a4 8
#define R_a5 9
#define R_v6 10
#define R_v7 11
#define R_t0 12
#define R_t1 13
#define R_t2 14
#define R_t3 15
#define R_s0 16
#define R_s1 17
#define R_s2 18
#define R_s3 19
#define R_s4 20
#define R_s5 21
#define R_s6 22
#define R_s7 23
#define R_t8 24
#define R_t9 25
#define R_k0 26
#define R_k1 27
#define R_gp 28
#define R_sp 29
#define R_s8 30
#define R_ra 31
/* VFPU registers, Quadword addressing */
#define Q_C000 0 /* First digit specifies matrix, second the row */
#define Q_C010 1
#define Q_C020 2
#define Q_C030 3
#define Q_C100 4
#define Q_C110 5
#define Q_C120 6
#define Q_C130 7
#define Q_C200 8
#define Q_C210 9
#define Q_C220 10
#define Q_C230 11
#define Q_C300 12
#define Q_C310 13
#define Q_C320 14
#define Q_C330 15
#define Q_C400 16
#define Q_C410 17
#define Q_C420 18
#define Q_C430 19
#define Q_C500 20
#define Q_C510 21
#define Q_C520 22
#define Q_C530 23
#define Q_C600 24
#define Q_C610 25
#define Q_C620 26
#define Q_C630 27
#define Q_C700 28
#define Q_C710 29
#define Q_C720 30
#define Q_C730 31
#define Q_R000 32 /* First Digit specifies matrix, third the column */
#define Q_R001 33
#define Q_R002 34
#define Q_R003 35
#define Q_R100 36
#define Q_R101 37
#define Q_R102 38
#define Q_R103 39
#define Q_R200 40
#define Q_R201 41
#define Q_R202 42
#define Q_R203 43
#define Q_R300 44
#define Q_R301 45
#define Q_R302 46
#define Q_R303 47
#define Q_R400 48
#define Q_R401 49
#define Q_R402 50
#define Q_R403 51
#define Q_R500 52
#define Q_R501 53
#define Q_R502 54
#define Q_R503 55
#define Q_R600 56
#define Q_R601 57
#define Q_R602 58
#define Q_R603 59
#define Q_R700 60
#define Q_R701 61
#define Q_R702 62
#define Q_R703 63
/* VFPU registers, 4x4 Matrix (Quad) addressing */
#define Q_M000 0 /* First digit specifies matrix */
#define Q_M100 4
#define Q_M200 8
#define Q_M300 12
#define Q_M400 16
#define Q_M500 20
#define Q_M600 24
#define Q_M700 28
#define Q_E000 32
#define Q_E100 36
#define Q_E200 40
#define Q_E300 44
#define Q_E400 48
#define Q_E500 52
#define Q_E600 56
#define Q_E700 60
/*
+-------------+------------+---------+---------------------------------------+
|31 26|25 21|20 16|15 0 |
+-------------+------------+---------+---------------------------------------+
| opcode 0x8c | base[4-0] | rt[4-0] | offset[15-0] |
+-------------+------------+---------+---------------------------------------+
LoadWord Relative to Address in General Purpose Register
lw %rt, offset(%base)
%rt: GPR Target Register (0...31)
%base: GPR, specifies Source Address Base
offset: signed Offset added to Source Address Base
%rt <- word_at_address (offset + %base)
*/
#define lw(rt,offset,base) \
(0x8c000000 | ((base) << 21) | ((rt) << 16) | ((offset) & 0xffff))
/*
+-------------+------------+---------+---------------------------------------+
|31 26|25 21|20 16|15 0 |
+-------------+------------+---------+---------------------------------------+
| opcode 0xac | base[4-0] | rt[4-0] | offset[15-0] |
+-------------+------------+---------+---------------------------------------+
StoreWord Relative to Address in General Purpose Register
sw %rt, offset(%base)
%rt: GPR Target Register (0...31)
%base: GPR, specifies Source Address Base
offset: signed Offset added to Source Address Base
word_at_address (offset + %base) <- %rt
*/
#define sw(rt,offset,base) \
(0xac000000 | ((base) << 21) | ((rt) << 16) | ((offset) & 0xffff))
/*
+-------------+------------+---------+---------------------------------------+
|31 26|25 21|20 16|15 0 |
+-------------+------------+---------+---------------------------------------+
| opcode 0x42 | rs[4-0] | rt[4-0] | immediate |
+-------------+------------+---------+---------------------------------------+
Add Immediate Unsigned Word
addiu %rt, %rs, immediate
%rt: GPR Target Register (0...31)
%rs: GPR Source Register (0...31)
immediate: value added to Source Register
%rt <- %rs + sign_extended(immediate)
*/
#define addiu(rt,rs,immediate) \
(0x24000000 | ((rs) << 21) | ((rt) << 16) | ((immediate) & 0xffff))
/*
+-------------+-----------+---------+----------------------------+-----+-----+
|31 26|25 21|20 16|15 2 | 1 | 0 |
+-------------+-----------+---------+----------------------------+-----+-----+
| opcode 0xd8 | base[4-0] | vt[4-0] | offset[15-2] | 0 |vt[5]|
+-------------+-----------+---------+----------------------------+-----+-----+
LoadVector.Quadword Relative to Address in General Purpose Register
Final Address needs to be 64-byte aligned.
lv.q %vfpu_rt, offset(%base)
%fpu_rt: VFPU Vector Target Register (column0-31/row32-63)
%base: GPR, specifies Source Address Base
offset: signed Offset added to Source Address Base
fpu_vtr <- vector_at_address (offset + %gpr)
*/
#define lv_q(vfpu_rt,offset,base,cache_policy) \
(0xd8000000 | \
((base) << 21) | \
(((vfpu_rt) & 0x1f) << 16) | ((vfpu_vtreg) >> 4) | \
((offset) << 2) | \
((cache_policy) << 1))
/*
+-------------+-----------+---------+----------------------------+-----+-----+
|31 26|25 21|20 16|15 2 | 1 | 0 |
+-------------+-----------+---------+----------------------------+-----+-----+
| opcode 0xf8 | base[4-0] | vt[4-0] | offset[15-2] | c_p |vt[5]|
+-------------+-----------+---------+----------------------------+-----+-----+
StoreVector.Quadword Relative to Address in General Purpose Register
Final Address needs to be 64-byte aligned.
sv.q %vfpu_rt, offset(%base), cache_policy
%fpu_rt: VFPU Vector Target Register (column0-31/row32-63)
%base: specifies Source Address Base
offset: signed Offset added to Source Address Base
cache_policy: 0 = write-through, 1 = write-back
vector_at_address (offset + %gpr) <- fpu_vtr
*/
#define sv_q(vfpu_rt,offset,base,cache_policy) \
(0xf8000000 | \
((base) << 21) | \
(((vfpu_rt) & 0x1f) << 16) | ((vfpu_rt) >> 4) | \
((offset) << 2) | \
((cache_policy) << 1))
/*
+-------------------------------------------------------------+--------------+
|31 7 | 6 0 |
+-------------------------------------------------------------+--------------+
| opcode 0xd0060000 | vfpu_rt[6-0] |
+-------------------------------------------------------------+--------------+
SetVectorZero.Single/Pair/Triple/Quad
vzero.s %vfpu_rt ; Set 1 Vector Component to 0.0f
vzero.p %vfpu_rt ; Set 2 Vector Components to 0.0f
vzero.t %vfpu_rt ; Set 3 Vector Components to 0.0f
vzero.q %vfpu_rt ; Set 4 Vector Components to 0.0f
%vfpu_rt: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rt] <- 0.0f
*/
#define vzero_s(vfpu_rt) (0xd0060000 | (vfpu_rt))
#define vzero_p(vfpu_rt) (0xd0060080 | (vfpu_rt))
#define vzero_t(vfpu_rt) (0xd0068000 | (vfpu_rt))
#define vzero_q(vfpu_rt) (0xd0068080 | (vfpu_rt))
/*
+-------------------------------------------------------------+--------------+
|31 7 | 6 0 |
+-------------------------------------------------------------+--------------+
| opcode 0xd0070000 | vfpu_rt[6-0] |
+-------------------------------------------------------------+--------------+
SetVectorOne.Single/Pair/Triple/Quad
vone.s %vfpu_rt ; Set 1 Vector Component to 1.0f
vone.p %vfpu_rt ; Set 2 Vector Components to 1.0f
vone.t %vfpu_rt ; Set 3 Vector Components to 1.0f
vone.q %vfpu_rt ; Set 4 Vector Components to 1.0f
%vfpu_rt: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rt] <- 0.0f
*/
#define vone_s(vfpu_rt) (0xd0070000 | (vfpu_rt))
#define vone_p(vfpu_rt) (0xd0070080 | (vfpu_rt))
#define vone_t(vfpu_rt) (0xd0078000 | (vfpu_rt))
#define vone_q(vfpu_rt) (0xd0078080 | (vfpu_rt))
/*
+-------------------------------------------------------------+--------------+
|31 7 | 6 0 |
+-------------------------------------------------------------+--------------+
| opcode 0xf3868080 | vfpu_rt[6-0] |
+-------------------------------------------------------------+--------------+
SetMatrixZero.Single/Pair/Triple/Quad
vmzero.p %vfpu_rt ; Set 2x2 Submatrix to 0.0f
vmzero.t %vfpu_rt ; Set 3x3 Submatrix to 0.0f
vmzero.q %vfpu_rt ; Set 4x4 Matrix to 0.0f
%vfpu_rt: VFPU Matrix Target Register ([s|p|t|q]reg 0..127)
vfpu_mtx[%vfpu_rt] <- 0.0f
*/
#define vmzero_p(vfpu_rt) (0xf3860080 | (vfpu_rt))
#define vmzero_t(vfpu_rt) (0xf3868000 | (vfpu_rt))
#define vmzero_q(vfpu_rt) (0xf3868080 | (vfpu_rt))
/*
+-------------------------------------------------------------+--------------+
|31 7 | 6 0 |
+-------------------------------------------------------------+--------------+
| opcode 0xf3838080 | vfpu_rt[6-0] |
+-------------------------------------------------------------+--------------+
vmidt.p %vfpu_rt ; Set 2x2 Submatrix to Identity
vmidt.t %vfpu_rt ; Set 3x3 Submatrix to Identity
vmidt.q %vfpu_rt ; Set 4x4 Matrix to Identity
%vfpu_rt: VFPU Matrix Target Register ([s|p|t|q]reg 0..127)
vfpu_mtx[%vfpu_rt] <- identity matrix
*/
#define vmidt_p(vfpu_rt) (0xf3830080 | (vfpu_rt))
#define vmidt_t(vfpu_rt) (0xf3838000 | (vfpu_rt))
#define vmidt_q(vfpu_rt) (0xf3838080 | (vfpu_rt))
/* helpers for direct __asm__ use: */
#define _cgen_stringify(x) #x
#define cgen_stringify(x) _cgen_stringify(x)
#define cgen_asm(x) ".loc 1 " cgen_stringify(__LINE__) " 0\n\t.word " cgen_stringify(x) "\n\t"
#endif
|
main.c:
| Code: |
#include <pspkernel.h>
#include <pspdebug.h>
#include <pspctrl.h>
#include <pspdisplay.h>
#include "codegen.h"
/* XXX SDK BUG: In theory everything should work when main is running in userspace.
Unfortunately the PSP hangs if we register the exception handler in the _init constructor, so we need to
call pspDebugInstallErrorHandler() in main().
*/
PSP_MAIN_THREAD_ATTR(/*PSP_THREAD_ATTR_USER |*/ PSP_THREAD_ATTR_VFPU);
PSP_MODULE_INFO("VFPU-test", 0x1000, 1, 1);
static int exit_callback(int arg1, int arg2, void *common)
{
sceKernelExitGame();
return 0;
}
static int callback_thread (SceSize args, void *argp)
{
int cbid = sceKernelCreateCallback("Exit Callback", exit_callback, NULL);
sceKernelRegisterExitCallback(cbid);
sceKernelSleepThreadCB();
return 0;
}
/* Sets up the callback thread and returns its thread id */
static void setup_callbacks (void) __attribute__((constructor));
static void setup_callbacks (void)
{
int thid = sceKernelCreateThread("update_thread", callback_thread, 0x11, 0xFA0, THREAD_ATTR_USER, 0);
if (thid >= 0)
sceKernelStartThread(thid, 0, 0);
}
static void back_to_kernel (void) __attribute__((destructor));
static void back_to_kernel (void)
{
sceKernelExitGame();
}
static void exception_handler (PspDebugRegBlock *regs)
{
pspDebugScreenInit();
pspDebugScreenSetBackColor(0x00FF0000);
pspDebugScreenSetTextColor(0xFFFFFFFF);
pspDebugScreenClear();
pspDebugScreenPrintf("Exception Details:\n");
pspDebugDumpException(regs);
}
void vfpu_init (void)
{
__asm__ volatile (
cgen_asm(vmzero_q(Q_M000)) /* access register array as matrices for speed */
cgen_asm(vmzero_q(Q_M100))
cgen_asm(vmzero_q(Q_M200))
cgen_asm(vmzero_q(Q_M300))
cgen_asm(vmzero_q(Q_M400))
cgen_asm(vmzero_q(Q_M500))
cgen_asm(vmzero_q(Q_M600))
cgen_asm(vmzero_q(Q_M700))
);
}
void vfpu_save_regs (float vfpu_regs [32][4])
{
register void *ptr __asm__ ("a0") = vfpu_regs;
__asm__ volatile (
cgen_asm(sv_q(0, 0 * 4, R_a0, 0))
cgen_asm(sv_q(1, 1 * 4, R_a0, 0))
cgen_asm(sv_q(2, 2 * 4, R_a0, 0))
cgen_asm(sv_q(3, 3 * 4, R_a0, 0))
cgen_asm(sv_q(4, 4 * 4, R_a0, 0))
cgen_asm(sv_q(5, 5 * 4, R_a0, 0))
cgen_asm(sv_q(6, 6 * 4, R_a0, 0))
cgen_asm(sv_q(7, 7 * 4, R_a0, 0))
cgen_asm(sv_q(8, 8 * 4, R_a0, 0))
cgen_asm(sv_q(9, 9 * 4, R_a0, 0))
cgen_asm(sv_q(10, 10 * 4, R_a0, 0))
cgen_asm(sv_q(11, 11 * 4, R_a0, 0))
cgen_asm(sv_q(12, 12 * 4, R_a0, 0))
cgen_asm(sv_q(13, 13 * 4, R_a0, 0))
cgen_asm(sv_q(14, 14 * 4, R_a0, 0))
cgen_asm(sv_q(15, 15 * 4, R_a0, 0))
cgen_asm(sv_q(16, 16 * 4, R_a0, 0))
cgen_asm(sv_q(17, 17 * 4, R_a0, 0))
cgen_asm(sv_q(18, 18 * 4, R_a0, 0))
cgen_asm(sv_q(19, 19 * 4, R_a0, 0))
cgen_asm(sv_q(20, 20 * 4, R_a0, 0))
cgen_asm(sv_q(21, 21 * 4, R_a0, 0))
cgen_asm(sv_q(22, 22 * 4, R_a0, 0))
cgen_asm(sv_q(23, 23 * 4, R_a0, 0))
cgen_asm(sv_q(24, 24 * 4, R_a0, 0))
cgen_asm(sv_q(25, 25 * 4, R_a0, 0))
cgen_asm(sv_q(26, 26 * 4, R_a0, 0))
cgen_asm(sv_q(27, 27 * 4, R_a0, 0))
cgen_asm(sv_q(28, 28 * 4, R_a0, 0))
cgen_asm(sv_q(29, 29 * 4, R_a0, 0))
cgen_asm(sv_q(30, 30 * 4, R_a0, 0))
cgen_asm(sv_q(31, 31 * 4, R_a0, 0))
: "=r"(ptr) : "r"(ptr) : "memory");
}
void vfpu_diff (float r1 [32][4], float r2 [32][4])
{
int i, j;
for (i=0; i<32; i++) {
for (j=0; j<4; j++) {
if (r1[i][j] != r2[i][j])
break;
}
if (j<4)
pspDebugScreenPrintf("- %i: % 5.5f % 5.5f % 5.5f % 5.5f\n",
i, r1[i][0], r1[i][1], r1[i][2], r1[i][3]);
}
for (i=0; i<32; i++) {
for (j=0; j<4; j++) {
if (r1[i][j] != r2[i][j])
break;
}
if (j<4)
pspDebugScreenPrintf("+ %i: % 5.5f % 5.5f % 5.5f % 5.5f\n",
i, r2[i][0], r2[i][1], r2[i][2], r2[i][3]);
}
}
static float vfpu_regs0 [32][4] __attribute__((aligned(64)));
static float vfpu_regs1 [32][4] __attribute__((aligned(64)));
/**
* ok... this function is the place to actually try the behaviour of some yet-unknown instructions.
*/
void vfpu_testcase (void)
{
__asm__(cgen_asm(vmidt_q(Q_M100)));
}
int main (int argc, char **argv)
{
pspDebugInstallErrorHandler(exception_handler);
sceCtrlSetSamplingCycle(0);
sceCtrlSetSamplingMode(PSP_CTRL_MODE_DIGITAL);
pspDebugScreenInit();
pspDebugScreenPrintf("VFPU test -- vfpu_regs0 = %p, vfpu_regs1 = %p\n\n", vfpu_regs0, vfpu_regs1);
pspDebugScreenPrintf("press O to run VFPU testcase or X to trap into breakpoint\n\n");
vfpu_init();
while (1) {
SceCtrlData pad;
sceCtrlReadBufferPositive(&pad, 1);
if (pad.Buttons & PSP_CTRL_CIRCLE) {
vfpu_save_regs(vfpu_regs0);
vfpu_testcase();
vfpu_save_regs(vfpu_regs1);
vfpu_diff(vfpu_regs0, vfpu_regs1);
}
if (pad.Buttons & PSP_CTRL_CROSS)
asm("break\n"); /* Cause a break exception, to check that the exception handler works... */
sceDisplayWaitVblankStart();
}
return 0;
}
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compile and install by typing "make install". |
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MrMr[iCE]
Joined: 03 Oct 2005
Posts: 43
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| Posted: Mon Oct 03, 2005 4:57 pm Post subject: |
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| Thanks for the info holger. Im gonna try a few tests myself, Ill post any new findings as I go on. |
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holger
Joined: 18 Aug 2005
Posts: 204
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MrMr[iCE]
Joined: 03 Oct 2005
Posts: 43
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| Posted: Mon Oct 03, 2005 7:47 pm Post subject: |
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I *think* i got vmmul working.
| Code: |
/*
+--------------------------+--------------+--+--------------+-+--------------+
|31 23 | 22 16 |15| 14 8 |7| 6 0 |
+--------------------------+--------------+--+--------------+-+--------------+
| opcode 0xf0000080 (p) | vfpu_rt[6-0] | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xf0008000 (t) | vfpu_rt[6-0] | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xf0008080 (q) | vfpu_rt[6-0] | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+--------------------------+--------------+--+--------------+-+--------------+
vmmul.p %vfpu_rd, %vfpu_rs, %vfpu_rt ; multiply 2 2x2 Submatrices
vmmul.t %vfpu_rd, %vfpu_rs, %vfpu_rt ; multiply 2 3x3 Submatrices
vmmul.q %vfpu_rd, %vfpu_rs, %vfpu_rt ; multiply 2 4x4 Matrices
*/
#define vmmul_p(vfpu_rd, vfpu_rs, vfpu_rt) (0xf0000080 | (vfpu_rt << 16) | (vfpu_rs << 8) | (vfpu_rd))
#define vmmul_t(vfpu_rd, vfpu_rs, vfpu_rt) (0xf0008000 | (vfpu_rt << 16) | (vfpu_rs << 8) | (vfpu_rd))
#define vmmul_q(vfpu_rd, vfpu_rs, vfpu_rt) (0xf0008080 | (vfpu_rt << 16) | (vfpu_rs << 8) | (vfpu_rd))
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please test though, im very tired at the moment =)
working on vsin/vcos next, that might help resolve a lot of the other opcodes. |
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dot_blank
Joined: 28 Sep 2005
Posts: 498
Location: Brasil
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| Posted: Mon Oct 03, 2005 8:46 pm Post subject: |
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excellent documentation and
analysis of vfpu holger ;)
this is (imho) the single most
important coprocessor in the psp
you are doing a terrific work
of documenting registers and
instruction set (i especially like
your commenting ... mantissa and all :)
one question: could be usefull
to use gdb with your vfpu test ;)
_________________
10011011 00101010 11010111 10001001 10111010 |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Mon Oct 03, 2005 10:08 pm Post subject: |
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| MrMr[iCE] wrote: |
I *think* i got vmmul working.
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applied. |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Mon Oct 03, 2005 10:09 pm Post subject: |
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| Quote: |
one question: could be usefull
to use gdb with your vfpu test ;)
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I have no idea what would need to get done to implement VFPU support in gdb, and the current quick'n'dirty approach works with surprisingly fast turnaround cycles... on the long run full VFPU support in the toolchain, assembler and debugger would be definitely cool. |
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Warren
Joined: 24 Jan 2004
Posts: 173
Location: San Diego, CA
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| Posted: Tue Oct 04, 2005 3:44 am Post subject: |
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| holger wrote: |
I have no idea what would need to get done to implement VFPU support in gdb, and the current quick'n'dirty approach works with surprisingly fast turnaround cycles... on the long run full VFPU support in the toolchain, assembler and debugger would be definitely cool. |
Tyranid has already added support for VFPU instrs in gdb. I'm unfamiliar with GAS so I really have no clue how to add instrs to it properly or else i already would have done so. I might experiment over the next couple days though. |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Tue Oct 04, 2005 3:59 am Post subject: |
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btw, has anybody of you seen some hints how one may catch VFPU exceptions? Or, even better, disable or avoid them at all?
When loading bitfields using the lv.q insn, e.g. the (unsigned long) testvector in the SVN testcase, it seems that in some cases an exception is thrown when the number is NaN and the PSP then locks up. But since there is a way to convert byte, short and integer numbers to float, there also must be some way to load them... |
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mrbrown
Joined: 17 Jan 2004
Posts: 1536
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| Posted: Tue Oct 04, 2005 6:03 am Post subject: |
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| Warren wrote: | | Tyranid has already added support for VFPU instrs in gdb. I'm unfamiliar with GAS so I really have no clue how to add instrs to it properly or else i already would have done so. I might experiment over the next couple days though. |
Does the GDB stub support VFPU registers? If not, single-stepping VFPU instructions is pretty much useless. |
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Warren
Joined: 24 Jan 2004
Posts: 173
Location: San Diego, CA
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| Posted: Tue Oct 04, 2005 6:05 am Post subject: |
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| mrbrown wrote: | | Does the GDB stub support VFPU registers? If not, single-stepping VFPU instructions is pretty much useless. |
It currently does not support dumping VFPU registers. |
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MrMr[iCE]
Joined: 03 Oct 2005
Posts: 43
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| Posted: Tue Oct 04, 2005 9:57 am Post subject: |
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|
some more functions that ive tested:
| Code: |
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd0100000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0100080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd0108000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0108080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
Reciprocal.Single/Pair/Triple/Quad
vrcp.s %vfpu_rd, %vfpu_rs ; calculate reciprocal (1/z) on single
vrcp.p %vfpu_rd, %vfpu_rs ; calculate reciprocal (1/z) on pair
vrcp.t %vfpu_rd, %vfpu_rs ; calculate reciprocal (1/z) on triple
vrcp.q %vfpu_rd, %vfpu_rs ; calculate reciprocal (1/z) on quad
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- 1.0 / vfpu_regs[%vfpu_rs]
*/
#define vrcp_s(vfpu_rd, vfpu_rs) (0xd0100000 | (vfpu_rs << 8) | (vfpu_rd))
#define vrcp_p(vfpu_rd, vfpu_rs) (0xd0100080 | (vfpu_rs << 8) | (vfpu_rd))
#define vrcp_t(vfpu_rd, vfpu_rs) (0xd0108000 | (vfpu_rs << 8) | (vfpu_rd))
#define vrcp_q(vfpu_rd, vfpu_rs) (0xd0108080 | (vfpu_rs << 8) | (vfpu_rd))
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd0140000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0140080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd0148000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0148080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
Exp2.Single/Pair/Triple/Quad (calculate 2 raised to the specified real number)
vexp2.s %vfpu_rd, %vfpu_rs ; calculate 2 ** y
vexp2.p %vfpu_rd, %vfpu_rs ; calculate 2 ** y
vexp2.t %vfpu_rd, %vfpu_rs ; calculate 2 ** y
vexp2.q %vfpu_rd, %vfpu_rs ; calculate 2 ** y
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- 2^(vfpu_regs[%vfpu_rs])
*/
#define vexp2_s(vfpu_rd, vfpu_rs) (0xd0140000 | (vfpu_rs << 8) | (vfpu_rd))
#define vexp2_p(vfpu_rd, vfpu_rs) (0xd0140080 | (vfpu_rs << 8) | (vfpu_rd))
#define vexp2_t(vfpu_rd, vfpu_rs) (0xd0148000 | (vfpu_rs << 8) | (vfpu_rd))
#define vexp2_q(vfpu_rd, vfpu_rs) (0xd0148080 | (vfpu_rs << 8) | (vfpu_rd))
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd0150000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0150080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd0158000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0158080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
Log2.Single/Pair/Triple/Quad (calculate logarithm base 2 of the specified real number)
vlog2.s %vfpu_rd, %vfpu_rs
vlog2.p %vfpu_rd, %vfpu_rs
vlog2.t %vfpu_rd, %vfpu_rs
vlog2.q %vfpu_rd, %vfpu_rs
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- log2(vfpu_regs[%vfpu_rs])
*/
#define vlog2_s(vfpu_rd, vfpu_rs) (0xd0150000 | (vfpu_rs << 8) | (vfpu_rd))
#define vlog2_p(vfpu_rd, vfpu_rs) (0xd0150080 | (vfpu_rs << 8) | (vfpu_rd))
#define vlog2_t(vfpu_rd, vfpu_rs) (0xd0158000 | (vfpu_rs << 8) | (vfpu_rd))
#define vlog2_q(vfpu_rd, vfpu_rs) (0xd0158080 | (vfpu_rs << 8) | (vfpu_rd))
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd0160000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0160080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd0168000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0168080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
SquareRoot.Single/Pair/Triple/Quad
vsqrt.s %vfpu_rd, %vfpu_rs ; calculate square root
vsqrt.p %vfpu_rd, %vfpu_rs ; calculate square root
vsqrt.t %vfpu_rd, %vfpu_rs ; calculate square root
vsqrt.q %vfpu_rd, %vfpu_rs ; calculate square root
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- sqrt(vfpu_regs[%vfpu_rs])
*/
#define vsqrt_s(vfpu_rd, vfpu_rs) (0xd0160000 | (vfpu_rs << 8) | (vfpu_rd))
#define vsqrt_p(vfpu_rd, vfpu_rs) (0xd0160080 | (vfpu_rs << 8) | (vfpu_rd))
#define vsqrt_t(vfpu_rd, vfpu_rs) (0xd0168000 | (vfpu_rs << 8) | (vfpu_rd))
#define vsqrt_q(vfpu_rd, vfpu_rs) (0xd0168080 | (vfpu_rs << 8) | (vfpu_rd))
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MrMr[iCE]
Joined: 03 Oct 2005
Posts: 43
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| Posted: Tue Oct 04, 2005 3:23 pm Post subject: |
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and here comes another run of ops ive tested:
| Code: |
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd0110000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0110080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd0118000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0118080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
ReciprocalSquareRoot.Single/Pair/Triple/Quad
vrsq.s %vfpu_rd, %vfpu_rs ; calculate reciprocal sqrt (1/sqrt(x)) on single
vrsq.p %vfpu_rd, %vfpu_rs ; calculate reciprocal sqrt (1/sqrt(x)) on pair
vrsq.t %vfpu_rd, %vfpu_rs ; calculate reciprocal sqrt (1/sqrt(x)) on triple
vrsq.q %vfpu_rd, %vfpu_rs ; calculate reciprocal sqrt (1/sqrt(x)) on quad
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- 1.0 / sqrt(vfpu_regs[%vfpu_rs])
*/
#define vrsq_s(vfpu_rd, vfpu_rs) (0xd0110000 | (vfpu_rs << 8) | (vfpu_rd))
#define vrsq_p(vfpu_rd, vfpu_rs) (0xd0110080 | (vfpu_rs << 8) | (vfpu_rd))
#define vrsq_t(vfpu_rd, vfpu_rs) (0xd0118000 | (vfpu_rs << 8) | (vfpu_rd))
#define vrsq_q(vfpu_rd, vfpu_rs) (0xd0118080 | (vfpu_rs << 8) | (vfpu_rd))
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd0120000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0120080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd0128000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0128080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
Sinus.Single/Pair/Triple/Quad
vsin.s %vfpu_rd, %vfpu_rs ; calculate sin on single
vsin.p %vfpu_rd, %vfpu_rs ; calculate sin on pair
vsin.t %vfpu_rd, %vfpu_rs ; calculate sin on triple
vsin.q %vfpu_rd, %vfpu_rs ; calculate sin on quad
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- sin(vfpu_regs[%vfpu_rs])
Note by John Kelley: trig functions on the vfpu expect input values
like vsin(degrees/90) or vsin(2/PI * radians)
*/
#define vsin_s(vfpu_rd, vfpu_rs) (0xd0120000 | (vfpu_rs << 8) | (vfpu_rd))
#define vsin_p(vfpu_rd, vfpu_rs) (0xd0120080 | (vfpu_rs << 8) | (vfpu_rd))
#define vsin_t(vfpu_rd, vfpu_rs) (0xd0128000 | (vfpu_rs << 8) | (vfpu_rd))
#define vsin_q(vfpu_rd, vfpu_rs) (0xd0128080 | (vfpu_rs << 8) | (vfpu_rd))
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd0130000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0130080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd0138000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0138080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
Cosine.Single/Pair/Triple/Quad
vcos.s %vfpu_rd, %vfpu_rs ; calculate cos on single
vcos.p %vfpu_rd, %vfpu_rs ; calculate cos on pair
vcos.t %vfpu_rd, %vfpu_rs ; calculate cos on triple
vcos.q %vfpu_rd, %vfpu_rs ; calculate cos on quad
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- cos(vfpu_regs[%vfpu_rs])
Note by John Kelley: trig functions on the vfpu expect input values
like vsin(degrees/90) or vsin(2/PI * radians)
*/
#define vcos_s(vfpu_rd, vfpu_rs) (0xd0130000 | (vfpu_rs << 8) | (vfpu_rd))
#define vcos_p(vfpu_rd, vfpu_rs) (0xd0130080 | (vfpu_rs << 8) | (vfpu_rd))
#define vcos_t(vfpu_rd, vfpu_rs) (0xd0138000 | (vfpu_rs << 8) | (vfpu_rd))
#define vcos_q(vfpu_rd, vfpu_rs) (0xd0138080 | (vfpu_rs << 8) | (vfpu_rd))
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd0170000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0170080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd0178000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0178080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
ArcSin.Single/Pair/Triple/Quad
vasin.s %vfpu_rd, %vfpu_rs ; calculate arcsin
vasin.p %vfpu_rd, %vfpu_rs ; calculate arcsin
vasin.t %vfpu_rd, %vfpu_rs ; calculate arcsin
vasin.q %vfpu_rd, %vfpu_rs ; calculate arcsin
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- arcsin(vfpu_regs[%vfpu_rs])
*/
#define vasin_s(vfpu_rd, vfpu_rs) (0xd0170000 | (vfpu_rs << 8) | (vfpu_rd))
#define vasin_p(vfpu_rd, vfpu_rs) (0xd0170080 | (vfpu_rs << 8) | (vfpu_rd))
#define vasin_t(vfpu_rd, vfpu_rs) (0xd0178000 | (vfpu_rs << 8) | (vfpu_rd))
#define vasin_q(vfpu_rd, vfpu_rs) (0xd0178080 | (vfpu_rs << 8) | (vfpu_rd))
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd0180000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0180080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd0188000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd0188080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
NegativeReciprocal.Single/Pair/Triple/Quad
vnrcp.s %vfpu_rd, %vfpu_rs ; calculate negative reciprocal
vnrcp.p %vfpu_rd, %vfpu_rs ; calculate negative reciprocal
vnrcp.t %vfpu_rd, %vfpu_rs ; calculate negative reciprocal
vnrcp.q %vfpu_rd, %vfpu_rs ; calculate negative reciprocal
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- -1/vfpu_regs[%vfpu_rs]
*/
#define vnrcp_s(vfpu_rd, vfpu_rs) (0xd0180000 | (vfpu_rs << 8) | (vfpu_rd))
#define vnrcp_p(vfpu_rd, vfpu_rs) (0xd0180080 | (vfpu_rs << 8) | (vfpu_rd))
#define vnrcp_t(vfpu_rd, vfpu_rs) (0xd0188000 | (vfpu_rs << 8) | (vfpu_rd))
#define vnrcp_q(vfpu_rd, vfpu_rs) (0xd0188080 | (vfpu_rs << 8) | (vfpu_rd))
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd01a0000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd01a0080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd01a8000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd01a8080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
NegativeSin.Single/Pair/Triple/Quad
vnsin.s %vfpu_rd, %vfpu_rs ; calculate negative sin
vnsin.p %vfpu_rd, %vfpu_rs ; calculate negative sin
vnsin.t %vfpu_rd, %vfpu_rs ; calculate negative sin
vnsin.q %vfpu_rd, %vfpu_rs ; calculate negative sin
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- sqrt(vfpu_regs[%vfpu_rs])
*/
#define vnsin_s(vfpu_rd, vfpu_rs) (0xd01a0000 | (vfpu_rs << 8) | (vfpu_rd))
#define vnsin_p(vfpu_rd, vfpu_rs) (0xd01a0080 | (vfpu_rs << 8) | (vfpu_rd))
#define vnsin_t(vfpu_rd, vfpu_rs) (0xd01a8000 | (vfpu_rs << 8) | (vfpu_rd))
#define vnsin_q(vfpu_rd, vfpu_rs) (0xd01a8080 | (vfpu_rs << 8) | (vfpu_rd))
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd01c0000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd01c0080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd01c8000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd01c8080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
ReciprocalExp2.Single/Pair/Triple/Quad
vrexp2.s %vfpu_rd, %vfpu_rs ; calculate 1/(2^y)
vrexp2.p %vfpu_rd, %vfpu_rs ; calculate 1/(2^y)
vrexp2.t %vfpu_rd, %vfpu_rs ; calculate 1/(2^y)
vrexp2.q %vfpu_rd, %vfpu_rs ; calculate 1/(2^y)
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- 1/exp2(vfpu_regs[%vfpu_rs])
*/
#define vrexp2_s(vfpu_rd, vfpu_rs) (0xd01c0000 | (vfpu_rs << 8) | (vfpu_rd))
#define vrexp2_p(vfpu_rd, vfpu_rs) (0xd01c0080 | (vfpu_rs << 8) | (vfpu_rd))
#define vrexp2_t(vfpu_rd, vfpu_rs) (0xd01c8000 | (vfpu_rs << 8) | (vfpu_rd))
#define vrexp2_q(vfpu_rd, vfpu_rs) (0xd01c8080 | (vfpu_rs << 8) | (vfpu_rd))
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please note that the sin/cos functions expect certain values. John Kelly pointed out you should pass in values like (degress/90.0) or (2/PI * radians) |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Tue Oct 04, 2005 5:28 pm Post subject: |
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| Code: |
/*
+-----------------------------------------+--+--------------+-+--------------+
|31 16 |15| 14 8 |7| 6 0 |
+-----------------------------------------+--+--------------+-+--------------+
| opcode 0xd01a0000 (s) | 0| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd01a0080 (p) | 0| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
| opcode 0xd01a8000 (t) | 1| vfpu_rs[6-0] |0| vfpu_rd[6-0] |
| opcode 0xd01a8080 (q) | 1| vfpu_rs[6-0] |1| vfpu_rd[6-0] |
+-----------------------------------------+--+--------------+-+--------------+
NegativeSin.Single/Pair/Triple/Quad
vnsin.s %vfpu_rd, %vfpu_rs ; calculate negative sin
vnsin.p %vfpu_rd, %vfpu_rs ; calculate negative sin
vnsin.t %vfpu_rd, %vfpu_rs ; calculate negative sin
vnsin.q %vfpu_rd, %vfpu_rs ; calculate negative sin
%vfpu_rd: VFPU Vector Target Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- sqrt(vfpu_regs[%vfpu_rs])
*/
|
are you sure about this one? Shouldn't this read
| Code: |
vfpu_regs[%vfpu_rd] <- -sin(vfpu_regs[%vfpu_rs])
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?
All other insns are added to SVN. |
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MrMr[iCE]
Joined: 03 Oct 2005
Posts: 43
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| Posted: Tue Oct 04, 2005 7:11 pm Post subject: |
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heh my bad, copy n paste can be evil sometimes =)
got one more, and I'm done for today. Will resume more ops tomorrow.
| Code: |
+------------------------+------------------+----+--------+---+--------------+
|31 21 | 20 16 | 15 | 14 8 | 7 | 6 0 |
+------------------------+------------------+----+--------+---+--------------+
| opcode 0xd06 (s) | constant (0-31) | 0 | 0 | 0 | vfpu_rd[6-0] |
| opcode 0xd06 (p) | constant (0-31) | 0 | 0 | 1 | vfpu_rd[6-0] |
| opcode 0xd06 (t) | constant (0-31) | 1 | 0 | 0 | vfpu_rd[6-0] |
| opcode 0xd06 (q) | constant (0-31) | 1 | 0 | 1 | vfpu_rd[6-0] |
+------------------------+------------------+----+--------+---+--------------+
StoreConstant.Single/Pair/Triple/Quad
vcst.s %vfpu_rd, %a ; store constant into single
vcst.p %vfpu_rd, %a ; store constant into pair
vcst.t %vfpu_rd, %a ; store constant into triple
vcst.q %vfpu_rd, %a ; store constant into quad
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
%a: VFPU Constant ID Value
================ ==========================================
0 = n/a 0
1 = HUGE 340282346638528859811704183484516925440.0
2 = SQRT(2) 1.41421
3 = 1/SQRT(2) 0.70711
4 = 2/SQRT(PI) 1.12838
5 = 2/PI 0.63662
6 = 1/PI 0.31831
7 = PI/4 0.78540
8 = PI/2 1.57080
9 = PI 3.14159
10 = E 2,71828
11 = LOG2E 1.44270
12 = LOG10E 0.43429
13 = LN2 0.69315
14 = LN10 2.30259
15 = 2*PI 6.28319
16 = PI/6 0.52360
17 = LOG10TWO 0.30103
18 = LOG2TEN 3.32193
19 = SQRT(3)/2 0.86603
20-31 = n/a 0
vfpu_regs[%vfpu_rd] <- constants[%a]
*/
#define vcst_s(vfpu_rd, a) (0xd0600000 | ((a) << 16) | (vfpu_rd))
#define vcst_p(vfpu_rd, a) (0xd0600080 | ((a) << 16) | (vfpu_rd))
#define vcst_t(vfpu_rd, a) (0xd0608000 | ((a) << 16) | (vfpu_rd))
#define vcst_q(vfpu_rd, a) (0xd0608080 | ((a) << 16) | (vfpu_rd))
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Tue Oct 04, 2005 11:33 pm Post subject: |
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cool, added. constant n/a-zero seems to be Zero...
should we define symbolic defines for these values, we could use the same names as in binutils/opcodes/mips-dis.c ? maybe helpful, I suppose here is not much subject to change... |
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MrMr[iCE]
Joined: 03 Oct 2005
Posts: 43
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| Posted: Wed Oct 05, 2005 1:42 am Post subject: |
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We can use the ones in mips_dis.c, I only changed them here because it was not clear if some values where being divided, multiplied , etc.. Stuff like VFPU _SQRT3_2 doesnt say to me its sqrt(3)/2, it could be interpreted in many ways =)
I'm also thinking this could use a manual. something like the mips architecture manuals. Anyone feel up to the challenge? Now''s a good time to get started on that task =) |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Wed Oct 05, 2005 2:38 am Post subject: |
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mmhhh... we can rename them to make them more intuitive, but this would make transition between gas/objdump'd code and macro-generated code harder.
Poll: What would you prefer? (I'd go for the mips-dis.c names and add "VFPU_NULL" at index [0]... and you?)
about the manual: I like the idea... but have other priorities right now; for coding the include file is just fine, but as reference a well-formatted PDF including some prosa explaining the concepts and giving some help to beginners would definitely be cool! |
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mrbrown
Joined: 17 Jan 2004
Posts: 1536
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| Posted: Wed Oct 05, 2005 2:55 am Post subject: |
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There is no constant at index 0. Instead use vzero.x (and vone.x for 1). My vote is for using the mips-dis.c names (especially since the assembler already supports these).
stefan needs to bust his hump and get the register operand support working already :). |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Wed Oct 05, 2005 3:38 am Post subject: |
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well... the VFPU loads a zero, so we're only documenting it's behaviour - and redundant opcodes are more likely than an engineer not assigning the first constant in an array to some defined value - ;)
I added the defines named as in mips-dis.c. |
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MrMr[iCE]
Joined: 03 Oct 2005
Posts: 43
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mrbrown
Joined: 17 Jan 2004
Posts: 1536
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| Posted: Wed Oct 05, 2005 5:40 am Post subject: |
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| holger wrote: | well... the VFPU loads a zero, so we're only documenting it's behaviour - and redundant opcodes are more likely than an engineer not assigning the first constant in an array to some defined value - ;)
I added the defines named as in mips-dis.c. |
If it's "n/a" then I don't see how you can rely on it. There could be a newer revision of VFPU where that "undocumented" constant no longer resolves to 0. You don't gain anything over just using vzero. |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Wed Oct 05, 2005 7:03 am Post subject: |
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| mrbrown wrote: | | holger wrote: | well... the VFPU loads a zero, so we're only documenting it's behaviour - and redundant opcodes are more likely than an engineer not assigning the first constant in an array to some defined value - ;)
I added the defines named as in mips-dis.c. |
If it's "n/a" then I don't see how you can rely on it. There could be a newer revision of VFPU where that "undocumented" constant no longer resolves to 0. You don't gain anything over just using vzero. |
where does the n/a comes from? |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Wed Oct 05, 2005 7:13 am Post subject: |
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cool idea! |
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groepaz
Joined: 01 Sep 2005
Posts: 305
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| Posted: Wed Oct 05, 2005 7:14 am Post subject: |
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| Quote: |
I'm also thinking this could use a manual. something like the mips architecture manuals. Anyone feel up to the challenge? Now''s a good time to get started on that task =)
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catch me on irc and i'll send you a preview of the pdf i'm working on....i didnt add any vfpu stuff yet (there wasnt anything to add until some days ago :=P) but it'll be the next thing i'll do i guess :)
_________________
http://www.hitmen-console.org
http://hitmen.c02.at/files/yapspd/ |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Wed Oct 05, 2005 7:15 am Post subject: |
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| groepaz wrote: | | Quote: |
I'm also thinking this could use a manual. something like the mips architecture manuals. Anyone feel up to the challenge? Now''s a good time to get started on that task =)
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catch me on irc and i'll send you a preview of the pdf i'm working on....i didnt add any vfpu stuff yet (there wasnt anything to add until some days ago :=P) but it'll be the next thing i'll do i guess :) |
can you please send it by pm? or even better, post here, I'm quite sure there are other ones interested in a review, too? don't have an irc client installed... |
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mrbrown
Joined: 17 Jan 2004
Posts: 1536
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| Posted: Wed Oct 05, 2005 8:35 am Post subject: |
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| holger wrote: | | where does the n/a comes from? |
| Code: |
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
%a: VFPU Constant ID Value
================ ==========================================
0 = n/a 0
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My point was that just because constant index 0 resolves to 0 today doesn't mean it always will. vzero is the more obvious (and readable) way to store 0 into a register.
Besides the assembler will reject any made up name not in the list seen in mips-dis.c :). |
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MrMr[iCE]
Joined: 03 Oct 2005
Posts: 43
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| Posted: Wed Oct 05, 2005 9:02 am Post subject: |
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I typed n/a because in mips_dis.c, there is a list of strings for the VFPU constants, and nothing is defined for index 0, all thats there is ""
BTW the precision of the values I entered for vcst are not the full number (except for VFPU_HUGE). the test app I'm using limits float output to 5 decimals.
holger: more opcodes for ya
| Code: |
/*
+----------------------+--------------+----+--------------+---+--------------+
|31 23 | 22 16 | 15 | 14 8 | 7 | 6 0 |
+----------------------+--------------+----+--------------+---+--------------+
| opcode 0x60000000 | vfpu_rt[6-0] | | vfpu_rs[6-0] | | vfpu_rd[6-0] |
+----------------------+--------------+----+--------------+---+--------------+
VectorAdd.Single/Pair/Triple/Quad
vadd.s %vfpu_rd, %vfpu_rs, %vfpu_rt ; Add Single
vadd.p %vfpu_rd, %vfpu_rs, %vfpu_rt ; Add Pair
vadd.t %vfpu_rd, %vfpu_rs, %vfpu_rt ; Add Triple
vadd.q %vfpu_rd, %vfpu_rs, %vfpu_rt ; Add Quad
%vfpu_rt: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- vfpu_regs[%vfpu_rs] + vfpu_regs[%vfpu_rt]
*/
#define vadd_s(vfpu_rd,vfpu_rs,vfpu_rt) (0x60000000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vadd_p(vfpu_rd,vfpu_rs,vfpu_rt) (0x60000080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vadd_t(vfpu_rd,vfpu_rs,vfpu_rt) (0x60008000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vadd_q(vfpu_rd,vfpu_rs,vfpu_rt) (0x60008080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
/*
+----------------------+--------------+----+--------------+---+--------------+
|31 23 | 22 16 | 15 | 14 8 | 7 | 6 0 |
+----------------------+--------------+----+--------------+---+--------------+
| opcode 0x608 (s) | vfpu_rt[6-0] | 0 | vfpu_rs[6-0] | 0 | vfpu_rd[6-0] |
| opcode 0x608 (p) | vfpu_rt[6-0] | 0 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
| opcode 0x608 (t) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 0 | vfpu_rd[6-0] |
| opcode 0x608 (q) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
+----------------------+--------------+----+--------------+---+--------------+
VectorSub.Single/Pair/Triple/Quad
vsub.s %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Single
vsub.p %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Pair
vsub.t %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Triple
vsub.q %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Quad
%vfpu_rt: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- vfpu_regs[%vfpu_rs] - vfpu_regs[%vfpu_rt]
*/
#define vsub_s(vfpu_rd,vfpu_rs,vfpu_rt) (0x60800000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vsub_p(vfpu_rd,vfpu_rs,vfpu_rt) (0x60800080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vsub_t(vfpu_rd,vfpu_rs,vfpu_rt) (0x60808000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vsub_q(vfpu_rd,vfpu_rs,vfpu_rt) (0x60808080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
/*
+----------------------+--------------+----+--------------+---+--------------+
|31 23 | 22 16 | 15 | 14 8 | 7 | 6 0 |
+----------------------+--------------+----+--------------+---+--------------+
| opcode 0x638 (s) | vfpu_rt[6-0] | 0 | vfpu_rs[6-0] | 0 | vfpu_rd[6-0] |
| opcode 0x638 (p) | vfpu_rt[6-0] | 0 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
| opcode 0x638 (t) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 0 | vfpu_rd[6-0] |
| opcode 0x638 (q) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
+----------------------+--------------+----+--------------+---+--------------+
VectorDiv.Single/Pair/Triple/Quad
vdiv.s %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Single
vdiv.p %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Pair
vdiv.t %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Triple
vdiv.q %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Quad
%vfpu_rt: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- vfpu_regs[%vfpu_rs] / vfpu_regs[%vfpu_rt]
*/
#define vdiv_s(vfpu_rd,vfpu_rs,vfpu_rt) (0x63800000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vdiv_p(vfpu_rd,vfpu_rs,vfpu_rt) (0x63800080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vdiv_t(vfpu_rd,vfpu_rs,vfpu_rt) (0x63808000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vdiv_q(vfpu_rd,vfpu_rs,vfpu_rt) (0x63808080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
/*
+----------------------+--------------+----+--------------+---+--------------+
|31 23 | 22 16 | 15 | 14 8 | 7 | 6 0 |
+----------------------+--------------+----+--------------+---+--------------+
| opcode 0x640 (s) | vfpu_rt[6-0] | 0 | vfpu_rs[6-0] | 0 | vfpu_rd[6-0] |
| opcode 0x640 (p) | vfpu_rt[6-0] | 0 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
| opcode 0x640 (t) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 0 | vfpu_rd[6-0] |
| opcode 0x640 (q) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
+----------------------+--------------+----+--------------+---+--------------+
VectorMul.Single/Pair/Triple/Quad
vmul.s %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Single
vmul.p %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Pair
vmul.t %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Triple
vmul.q %vfpu_rd, %vfpu_rs, %vfpu_rt ; Sub Quad
%vfpu_rt: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- vfpu_regs[%vfpu_rs] * vfpu_regs[%vfpu_rt]
*/
#define vmul_s(vfpu_rd,vfpu_rs,vfpu_rt) (0x64000000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vmul_p(vfpu_rd,vfpu_rs,vfpu_rt) (0x64000080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vmul_t(vfpu_rd,vfpu_rs,vfpu_rt) (0x64008000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vmul_q(vfpu_rd,vfpu_rs,vfpu_rt) (0x64008080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
/*
+----------------------+--------------+----+--------------+---+--------------+
|31 23 | 22 16 | 15 | 14 8 | 7 | 6 0 |
+----------------------+--------------+----+--------------+---+--------------+
| opcode 0x648 (p) | vfpu_rt[6-0] | 0 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
| opcode 0x648 (t) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 0 | vfpu_rd[6-0] |
| opcode 0x648 (q) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
+----------------------+--------------+----+--------------+---+--------------+
VectorDotProduct.Pair/Triple/Quad
vdot.p %vfpu_rd, %vfpu_rs, %vfpu_rt ; Dot Product Pair
vdot.t %vfpu_rd, %vfpu_rs, %vfpu_rt ; Dot Product Triple
vdot.q %vfpu_rd, %vfpu_rs, %vfpu_rt ; Dot Product Quad
%vfpu_rt: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- dotproduct(vfpu_regs[%vfpu_rs], vfpu_regs[%vfpu_rt])
*/
#define vdot_p(vfpu_rd,vfpu_rs,vfpu_rt) (0x64800080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vdot_t(vfpu_rd,vfpu_rs,vfpu_rt) (0x64808000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vdot_q(vfpu_rd,vfpu_rs,vfpu_rt) (0x64808080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
/*
+----------------------+--------------+----+--------------+---+--------------+
|31 23 | 22 16 | 15 | 14 8 | 7 | 6 0 |
+----------------------+--------------+----+--------------+---+--------------+
| opcode 0x660 (p) | vfpu_rt[6-0] | 0 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
| opcode 0x660 (t) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 0 | vfpu_rd[6-0] |
| opcode 0x660 (q) | vfpu_rt[6-0] | 1 | vfpu_rs[6-0] | 1 | vfpu_rd[6-0] |
+----------------------+--------------+----+--------------+---+--------------+
VectorHomogenousDotProduct.Pair/Triple/Quad
vhdp.p %vfpu_rd, %vfpu_rs, %vfpu_rt ; Dot Product Pair
vhdp.t %vfpu_rd, %vfpu_rs, %vfpu_rt ; Dot Product Triple
vhdp.q %vfpu_rd, %vfpu_rs, %vfpu_rt ; Dot Product Quad
%vfpu_rt: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rs: VFPU Vector Source Register ([s|p|t|q]reg 0..127)
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- homogenousdotproduct(vfpu_regs[%vfpu_rs], vfpu_regs[%vfpu_rt])
*/
#define vhdp_p(vfpu_rd,vfpu_rs,vfpu_rt) (0x66000080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vhdp_t(vfpu_rd,vfpu_rs,vfpu_rt) (0x66008000 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
#define vhdp_q(vfpu_rd,vfpu_rs,vfpu_rt) (0x66008080 | ((vfpu_rt) << 16) | ((vfpu_rs) << 8) | (vfpu_rd))
/*
+-------------------------------------------------------------+--------------+
|31 16 | 15 | 14 8 | 7 | 6 0 |
+-------------------------------------------------------------+--------------+
| opcode 0xd003 (p) | 0 | 0 | 1 | vfpu_rd[6-0] |
| opcode 0xd003 (t) | 1 | 0 | 0 | vfpu_rd[6-0] |
| opcode 0xd003 (q) | 1 | 0 | 1 | vfpu_rd[6-0] |
+-------------------------------------------------------------+--------------+
VectorLoadIdentity.Pair/Triple/Quad
vidt.p %vfpu_rd ; Set 2x1 Vector to Identity
vidt.t %vfpu_rd ; Set 3x1 Vector to Identity
vidt.q %vfpu_rd ; Set 4x1 Vector to Identity
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
vfpu_regs[%vfpu_rd] <- identity vector
*/
#define vidt_p(vfpu_rd) (0xd0030080 | (vfpu_rd))
#define vidt_t(vfpu_rd) (0xd0038000 | (vfpu_rd))
#define vidt_q(vfpu_rd) (0xd0038080 | (vfpu_rd))
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groepaz
Joined: 01 Sep 2005
Posts: 305
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| Posted: Wed Oct 05, 2005 9:20 am Post subject: |
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| Quote: |
can you please send it by pm? or even better, post here, I'm quite sure there are other ones interested in a review, too? don't have an irc client installed...
|
i will do, if anyone else wants it, leave me a pm.
i dont want to post the url to it publicly yet, since its still *very* much work in progress, contains outdated information in certain areas, and shouldnt be used by anyone who isnt exactly knowing how to use this kind of "guessed" information. oh well :) its the next thing i'll work on after cleaning up and releasing the pspinside source.
_________________
http://www.hitmen-console.org
http://hitmen.c02.at/files/yapspd/ |
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holger
Joined: 18 Aug 2005
Posts: 204
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| Posted: Wed Oct 05, 2005 6:11 pm Post subject: |
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| mrbrown wrote: | | holger wrote: | | where does the n/a comes from? |
| Code: |
%vfpu_rd: VFPU Vector Destination Register ([s|p|t|q]reg 0..127)
%a: VFPU Constant ID Value
================ ==========================================
0 = n/a 0
|
My point was that just because constant index 0 resolves to 0 today doesn't mean it always will. vzero is the more obvious (and readable) way to store 0 into a register.
Besides the assembler will reject any made up name not in the list seen in mips-dis.c :). |
well... we're the ones building the assembler, not? nevertheless... since you all seem to have serious doubts that the zero=0 guess is true, maybe we should rather remove this define... |
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