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[holger]

hi,

where are informations about the VFPU instruction set collected and documented? What is already supported by the toolchain, what is tested, what's known to work and what not?

[Warren]

No VFPU instructions are currently supported by the compiler. There is however, support for them in the disassembler.

I have been trying to get ahold of Stefan- for the past week without success to get an idea of his progress with VFPU instrs.

[AudioMonster]

I would also be extremely interested in those instructions :)

[holger]

[AudioMonster]

I am more interested in floating point matrixes multiplication and vector multiplications and additions. Is it already possible to use the VFPU to do that , at this point ?

[Warren]

Did you not see "No VFPU instructions are currently supported by the compiler"?

And by compiler I should have said assembler

[AudioMonster]

Yeah i don't care if the compiler does not support it ... as long as i can directly use it via assembly. Too bad :(

[stefan]

The disassembler should support all VFPU opcodes. The assembler is missing support for register operands, rotate operands, and macro instructions. The VFPU register syntax is extremely difficult to support, because there are many different variants that can be used depending on the instruction or context.

Without support for register operands the VFPU assembler is useless. I do not have a ETA on when assembler support will be finished.

[AudioMonster]

Stefan could you point me on any kind documentation regarding the VFPU ? Like the instruction set and so on ?

The VFPU and Virtual Mobile Engine are my 2 main items of interest on the PSP ! ( and i guess it's not tomorrow that we'll learn how to program the VME ).

[holger]

:) and I guess there is no public documentation -- we'll need to start to write it on our own...

[AudioMonster]

Looking at mips-opc.c :
http://svn.pspdev.org/filedetails.php?repname=psp&path=%2Ftrunk%2Fbinutils-psp%2Fopcodes%2Fmips-opc.c&rev=0&sc=0

i see all the VFPU opcodes that Stefan is talking about.

I have a few questions about them.
I am sorry if they sound moronic, but i am not familiar at all with FPU dedicated to 3D operations, and at this point, i have no fu..... manual to read :(
Feel free to point me out on some other kind of VFPU that may give me some clue about the PSP VFPU.

* How were the opcodes names determined ? Especially the non-obvious ones like vidt, vhtfm2, vbfy1, vhdp and so on ? Did you actually test the instruction, check what it did and gave it a name by yourself ?
* What do the .p .q .s .t which often follow the opcodes names mean ? Is it a way to select what group(s) of registers are used during the operation ? ( I've read there are 128 32bits registers ... )
* How to read the "args" part of each opcode entry in the file, like "?v7z,?s7y,?t7x" for vmmul.q ?

I am aware that i cannot use those instructions yet, but i could get a clue on what are the capabilities of the VFPU if someone can answer those questions. If you could even say more that wouldn't hurt :)

[AudioMonster]

Oh, and ... looking at the vadd instruction in particular, there are :

"vadd.q", "?d3d,?s3s,?t3t",
"vadd.t", "?d2d,?s2s,?t2t",
"vadd.p", "?d1d,?s1s,?t1t",
"vadd.s", "?d0d,?s0s,?t0t",

same for vmul, vsub, vdot and other basic operations.

So, are those .p .q .s .t actually refering to some independant units of the VFPU so it is possible to achieve 4 instructions in parallel ( one per unit ) ?

Would be great.

[ector]

i believe the s p t q mean single, pair, triplet, quad.
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[holger]

On a first glance a lot of the stuff looks a bit similiar like the SSE/SEE2 and Altivec instruction set, there seem to be some similiarities. The SSE spec is available for download on the Intel website, the Altivec one on the Motorola website (or was it IBM?). There is also a MIPS-3D SIMD instructions set spec available on mips.com, but I don't know this one.

Registers are usually 128 bit wide and can get accessed as 2 double words (64bit), 4 words (32bits), 8 short words (16bit), or 16 bytes, specified by the instruction suffix. Some instructions work on floats only, some on integer words.

Most instructions work in parallel on all words in the register (although there are exceptions, like masked and swizzle instructions). Usually SIMD instructions don't throw FPU exceptions, but the SIMD registers have seperate exception flags that either need to get checked manually or can get used by some of the conditional instructions (e.g. conditional moves).

[stefan]

The VFPU opcodes come from pspgcc_131.tgz that has been floating around for quite sometime. I didn't add them, mrbrown did. I just started working on the assembler after he dropped out of PSP homebrew. Information for the VFPU assembler comes from the same place, that's why it's so difficult to implement register operand support from reversed psp-gas code.

It's true the suffixes work on different size chunks of data - single, paired, triple, quad. The VFPU can only work with vectors (and matrices) of floats. It knows nothing about the classic SIMD types (16 bytes, 8 halfwords, 4 words, etc.). It cannot issue multiple instructions per operand size AFAIK. The registers are accessed in a specific configuration to give you vectors and matrices depending on the type of instruction or operand you use. You can use special prefix instructions to modify the data for an subsequent instruction, for example, you can "swizzle" the x, y, z, w from a source register before it's operated on.

Unless Sony releases VFPU documentation to the world (not likely) it will be up to the community to document this beast. Throw the SSE/SSE2 and Altivec manual out the window, it's next to useless.