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ME cpu has two unknown instructions

 
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hlide



Joined: 10 Sep 2006
Posts: 750

PostPosted: Thu Jan 11, 2007 6:30 am    Post subject: ME cpu has two unknown instructions Reply with quote

when looking at mips-opc.c i was intrigued to see them :
Code:

{ "ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3|AL },
{ "sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3|AL },

are "defined" for allegrex where as :
Code:

{ "ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
{ "sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },

are not "defined" for allegrex.

PSP is not a MIPS64, so PSP shouldn't know those both instructions which are for unaligned doubleword load/store.

There is only one possibilty : ldl/sdl are special instructions which have a different goal.

Indeed they seem to be used a lot on ME processor, just one example :

Code:

sub0(arg1, arg2, arg3):
        addiu      $sp, $sp, -0x10
        sw         $ra, 0xC($sp)
        sw         $s2, 0x8($sp)
        move       $s2, $a2
        sw         $s1, 0x4($sp)
        move       $s1, $a1
        sw         $s0, 0x0($sp)
        move       $s0, $a0
        move       $a0, $zr         # int timeout = 0;

0:      ldl        $a1, 0x200($a3)  # loop: ready = vme_bus[0x200]; (?)
        addiu      $a0, $a0, 0x1    # timeout++;
        andi       $v0, $a1, 0x1
        bnez       $v0, 1f          # if (ready & 1) goto goon;
        slti       $v1, $a0, 0x1000
        bnez       $v1, 0b          # if (timeout < 0x1000) goto loop; 
        nop       
        jal        sub1             # sub1(0xD); // reset ?
        li         $a0, 0xD

1:      sdl        $s0, 0x200($a3)  # goon: vme_bus[0x200] = arg1; (?)
        sdl        $s1, 0x201($a3)  #       vme_bus[0x201] = arg2; (?)
        sdl        $s2, 0x202($a3)  #       vme_bus[0x202] = arg3; (?)
        move       $v0, $zr
        sdl        $v0, 0x203($a3)  #       vme_bus[0x203] = 0; (?)
        lw         $ra, 0xC($sp)
        lw         $s2, 0x8($sp)
        lw         $s1, 0x4($sp)
        lw         $s0, 0x0($sp)
        jr         $ra
        addiu      $sp, $sp, 0x10


two remarks :

- $a3 is a dummy register so i suspect those instruction not to have a base register (their base opcodes seem to be more like 0x68E00000 and 0xB0E00000 than 0x68000000 and 0xB0000000)
- the offset should probably be an immediate (the biggest value I found out is 0x58F, which an immediate value encoded less than 12 bits).

so i suspect those both instructions to be something like :

ldl $v0, 0x200($a3) ==> mfvme $v0, $200 <=> $v0 = vme_bus[0x200]
sdl $v0, 0x200($a3) ==> mtvme $v0, $200 <=> vme_bus[0x200] = $v0

is it for VME ? is it for AVC decoder ? dunno.
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adrahil



Joined: 16 Mar 2006
Posts: 277

PostPosted: Thu Jan 11, 2007 8:10 am    Post subject: Reply with quote

Very interesting stuff :)
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