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[jsgf]

I've been picking through the VFPU binutils patch and correlating it with the stuff hinted at in the BP05 presentation. There's a pile of interesting stuff in there that we haven't even started scratching at yet.

I don't know if anyone has looked into this yet, but since Chp's vfpu gum doesn't make use of this stuff, I assume it isn't common knowledge.

Prefixes

Each VPU instruction can have up to 3 prefixes which specify transformations which are performed on the two inputs and the output. These are:

Swizzling, which allows you to select which parts of an input vector you want to operate on. For example:

[chp]

Ahh, nice, so that's what the vrot op was for. :) I've tried this on the rotate-functions and it works just fine! The question is if it's faster to use this, or if the previous approach with generating single values is the way to go. I'll do some tests for this.
_________________
GE Dominator

[jsgf]

You could do something like:

[korskarn]

For input registers, the VFPU also supports absolute values and negative absolute values. I don't know if the homebrew binutils supports the absolute values, but the hardware does.

In the constants that can be used, 1/6 is also available.


About the vrot functions, multiple sines are possible (but only one cosine):
you can have either 1 cosine, 1 sine and 2 zeros, or 1 cosine with 3 sines.

Not all sine and cosine combinations are possible. These are the restrictions:

- There is only 1 cosine
- There is always either 1 or 3 sine (can't have cosine only, or 1 cosine and 2 sine)
- Cosine is always positive
- If there are 3 sines, they are always all positive or all negative, can't have some positive and some negative.

These restrictions lead to the 32 following combinations (its enconded on 5 bits):

[ C, S, S, S]
[ S, C, 0, 0]
[ S, 0, C, 0]
[ S, 0, 0, C]
[ C, S, 0, 0]
[ S, C, S, S]
[ 0, S, C, 0]
[ 0, S, 0, C]
[ C, 0, S, 0]
[ 0, C, S, 0]
[ S, S, C, S]
[ 0, 0, S, C]
[ C, 0, 0, S]
[ 0, C, 0, S]
[ 0, 0, C, S]
[ S, S, S, C]

And repeat the same 16 combinations but with all sines negative

Like you said, the input is scalar, only the X component is used.

The unit used for angle is quarters of a whole turn, meaning that 1.0 is 90 degrees or pi/2 radians.

In terms of performance, the vrot has a latency of 8 cycles and a pitch of 2 cycles, so filling a rotation matrix with 2 vrot instructions sould take between 4 and 12 cycles depending on what follows the second vrot (there will be no pipeline stall if the next instruction has a latency of 8 or more cycles and if the next instruction does not use the result of the last vrot).

The vmul instruction has a latency of 5 with a pitch of 1
Since the vmul has a lower latency than the vrot, you will have a 3 cycles stall between
the vrot and the vmul, and in the end, the result of the vmul gets written exactly at the same time as a second vrot would. But, since the mult has a lower latency and pitch than the vrot, the next instruction has less chances to get stalled.
EDIT: I overlooked something... since the vmul instruction depends on the result of the vrot, it will be stalled untill the result of the vrot gets written and thus take longer than 2 vrot, unless you can interleave other instructions between the vrot and the vmul, in which case the vmul might be faster than a second vrot.
All depends if the instructions are poorly scheduled or well optimized for the pipeline!

The pipeline rules with the stalls, latency and pitch are the following:
An instruction has several stages, among others fethcing the registers, execution, etc. The last stage is writing the result to the destination register, and regardless of the dependencies, an instruction write stage can occur only AFTER the previous instruction's write stage has completed. So, if an instruction with a lower latency follows one with a higer latency, the end of the second instruction will always be one cycle after the previous instruction, no amtter if it is really fast to execute.
The pitch is the number of cycles between the execution stage of this instruction and the execution stage of the next. So we can say it is the real number of cycle the instruction takes if there are no other stalls.

[jsgf]

I forgot to mention it, but abs is supported: [|x|, |y|, ...].

[korskarn]

[jsgf]

[chp]

I wasn't sure what they did, but I had my ideas... I was experimenting with lvl and lvr earlier but they locked up, but I guess I was using them incorrectly... I'll take a look at them!
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GE Dominator

[chp]

Ok, I've submitted some new code in GUM that's based on this thread... ulv & usv works just great. Also, lv.s/sv.s do not require more than 4 bytes of alignment it seems (as I suspected before), so I killed those unecessary aligns too.

The data-functions does not seem to support masking/etc however (which is quite understandable I guess).
_________________
GE Dominator

[korskarn]